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[ DevCourseWeb.com ] Udemy - Learn Vivado from Top to Bottom - Your Complete Guide

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698

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937.96MB

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2022-01-11

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DevCourseWeb com Udemy Learn Vivado from Top to Bottom Your Complete Guide

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File Name

Size

Get Bonus Downloads Here.url

182B

~Get Your Files Here !/01 - Introduction/001 Welcome to the Course.mp4

25.11MB

~Get Your Files Here !/01 - Introduction/001 Welcome to the Course_en.srt

2.93KB

~Get Your Files Here !/01 - Introduction/002 Introduction to the Vivado Tool Suite.mp4

21.67MB

~Get Your Files Here !/01 - Introduction/002 Introduction to the Vivado Tool Suite_en.srt

2.3KB

~Get Your Files Here !/01 - Introduction/003 Vivado Download and Installation.mp4

22.08MB

~Get Your Files Here !/01 - Introduction/003 Vivado Download and Installation_en.srt

8.67KB

~Get Your Files Here !/01 - Introduction/004 Supported FPGAs and Development Boards.html

5.14KB

~Get Your Files Here !/01 - Introduction/external-assets-links.txt

197B

~Get Your Files Here !/02 - Vivado Basics/001 Opening Vivado.mp4

6.8MB

~Get Your Files Here !/02 - Vivado Basics/001 Opening Vivado_en.srt

3.86KB

~Get Your Files Here !/02 - Vivado Basics/002 Creating a New Project in Vivado.mp4

7.43MB

~Get Your Files Here !/02 - Vivado Basics/002 Creating a New Project in Vivado_en.srt

2.71KB

~Get Your Files Here !/02 - Vivado Basics/003 Importing a Xilinx ISE Project Into Vivado.mp4

12.06MB

~Get Your Files Here !/02 - Vivado Basics/003 Importing a Xilinx ISE Project Into Vivado_en.srt

4.72KB

~Get Your Files Here !/02 - Vivado Basics/004 Create a Project From a Predefined Template.mp4

8.24MB

~Get Your Files Here !/02 - Vivado Basics/004 Create a Project From a Predefined Template_en.srt

2.77KB

~Get Your Files Here !/02 - Vivado Basics/005 Vivado Example Project.mp4

13.68MB

~Get Your Files Here !/02 - Vivado Basics/005 Vivado Example Project_en.srt

6.09KB

~Get Your Files Here !/02 - Vivado Basics/006 Add Existing Files to a Project.mp4

9.65MB

~Get Your Files Here !/02 - Vivado Basics/006 Add Existing Files to a Project_en.srt

3.75KB

~Get Your Files Here !/02 - Vivado Basics/007 Creating New Files.mp4

12.76MB

~Get Your Files Here !/02 - Vivado Basics/007 Creating New Files_en.srt

5.27KB

~Get Your Files Here !/02 - Vivado Basics/008 Working with Block Designs in Vivado.mp4

18.88MB

~Get Your Files Here !/02 - Vivado Basics/008 Working with Block Designs in Vivado_en.srt

7.53KB

~Get Your Files Here !/02 - Vivado Basics/009 Generating the FPGA Configuration File.mp4

11.69MB

~Get Your Files Here !/02 - Vivado Basics/009 Generating the FPGA Configuration File_en.srt

4.83KB

~Get Your Files Here !/02 - Vivado Basics/010 Programming Your Development Board.mp4

7.16MB

~Get Your Files Here !/02 - Vivado Basics/010 Programming Your Development Board_en.srt

2.83KB

~Get Your Files Here !/02 - Vivado Basics/011 Documentation Navigator.mp4

6.5MB

~Get Your Files Here !/02 - Vivado Basics/011 Documentation Navigator_en.srt

2.33KB

~Get Your Files Here !/02 - Vivado Basics/7_seg_project/7_seg.xdc

13.17KB

~Get Your Files Here !/02 - Vivado Basics/7_seg_project/Hex_to_7_Seg.vhd

1.11KB

~Get Your Files Here !/02 - Vivado Basics/7_seg_project/Hex_to_7_Seg_top.vhd

2.5KB

~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/Full_Adder_2.bld

1.05KB

~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/Full_Adder_2.cmd_log

1.04KB

~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/Full_Adder_2.gise

17.94KB

~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/Full_Adder_2.ibs

60.1KB

~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/Full_Adder_2.lso

~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/Full_Adder_2.ncd

2.92KB

~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/Full_Adder_2.ngc

1.3KB

~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/Full_Adder_2.ngd

2.48KB

~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/Full_Adder_2.ngr

1.16KB

~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/Full_Adder_2.pad

5.93KB

~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/Full_Adder_2.par

5.29KB

~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/Full_Adder_2.pcf

451B

~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/Full_Adder_2.prj

30B

~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/Full_Adder_2.ptwx

16.08KB

~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/Full_Adder_2.stx

~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/Full_Adder_2.syr

10.16KB

~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/Full_Adder_2.twr

2.55KB

~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/Full_Adder_2.twx

18.96KB

~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/Full_Adder_2.ucf

153B

~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/Full_Adder_2.unroutes

156B

~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/Full_Adder_2.ut

392B

~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/Full_Adder_2.vhd

971B

~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/Full_Adder_2.xdl

1.91KB

~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/Full_Adder_2.xise

32.39KB

~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/Full_Adder_2.xpi

46B

~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/Full_Adder_2.xst

1.13KB

~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/Full_Adder_2_bitgen.xwbt

306B

~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/Full_Adder_2_envsettings.html

15.66KB

~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/Full_Adder_2_fpga_editor.log

645B

~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/Full_Adder_2_guide.ncd

2.92KB

~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/Full_Adder_2_isim_beh.exe

117.5KB

~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/Full_Adder_2_isim_beh.wdb

3.65KB

~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/Full_Adder_2_map.map

2.65KB

~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/Full_Adder_2_map.mrp

5.77KB

~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/Full_Adder_2_map.ncd

2.25KB

~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/Full_Adder_2_map.ngm

4.53KB

~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/Full_Adder_2_map.xrpt

12.27KB

~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/Full_Adder_2_ngdbuild.xrpt

5.44KB

~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/Full_Adder_2_pad.csv

5.96KB

~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/Full_Adder_2_pad.txt

26.43KB

~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/Full_Adder_2_par.xrpt

59.6KB

~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/Full_Adder_2_stx_beh.prj

35B

~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/Full_Adder_2_summary.html

8.6KB

~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/Full_Adder_2_summary.xml

408B

~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/Full_Adder_2_usage.xml

5.82KB

~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/Full_Adder_2_vhdl.prj

81B

~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/Full_Adder_2_xst.xrpt

11.09KB

~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/_ngo/netlist.lst

84B

~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/_xmsgs/bitgen.xmsgs

367B

~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/_xmsgs/ibiswriter.xmsgs

589B

~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/_xmsgs/map.xmsgs

741B

~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/_xmsgs/ngdbuild.xmsgs

367B

~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/_xmsgs/par.xmsgs

1KB

~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/_xmsgs/pn_parser.xmsgs

778B

~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/_xmsgs/trce.xmsgs

1.56KB

~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/_xmsgs/xdl.xmsgs

512B

~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/_xmsgs/xst.xmsgs

625B

~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/compxlib.log

~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/full_adder_2.bgn

4.76KB

~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/full_adder_2.bit

71.06KB

~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/full_adder_2.drc

197B

~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/iseconfig/Full_Adder_2.projectmgr

8.65KB

~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/iseconfig/Full_Adder_2.xreport

20.64KB

~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/isim.cmd

44B

~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/pa.fromHdl.tcl

646B

~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/pa.fromNcd.tcl

1KB

~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/pepExtractor.prj

25B

~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/planAhead.ngc2edif.log

413B

~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/planAhead_run_1/Full_Adder_2.data/constrs_1/fileset.xml

361B

~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/planAhead_run_1/Full_Adder_2.data/runs/impl_1.psg

391B

~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/planAhead_run_1/Full_Adder_2.data/runs/runs.xml

190B

~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/planAhead_run_1/Full_Adder_2.data/sources_1/fileset.xml

547B

~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/planAhead_run_1/Full_Adder_2.data/wt/webtalk_pa.xml

1.38KB

~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/planAhead_run_1/Full_Adder_2.ppr

277B

~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/planAhead_run_1/planAhead.jou

1.48KB

~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/planAhead_run_1/planAhead.log

4.73KB

~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/planAhead_run_1/planAhead_run.log

1.03KB

~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/planAhead_run_4/Full_Adder_2.data/constrs_1/designprops.xml

365B

~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/planAhead_run_4/Full_Adder_2.data/constrs_1/fileset.xml

561B

~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/planAhead_run_4/Full_Adder_2.data/constrs_1/usercols.xml

78B

~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/planAhead_run_4/Full_Adder_2.data/sources_1/chipscope.xml

113B

~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/planAhead_run_4/Full_Adder_2.data/sources_1/fileset.xml

589B

~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/planAhead_run_4/Full_Adder_2.data/sources_1/ports.xml

253B

~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/planAhead_run_4/Full_Adder_2.data/wt/webtalk_pa.xml

1.41KB

~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/planAhead_run_4/Full_Adder_2.ppr

238B

~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/planAhead_run_4/planAhead.jou

1.74KB

~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/planAhead_run_4/planAhead.log

6.03KB

~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/planAhead_run_4/planAhead_run.log

726B

~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/test_Full_Adder_2.vhd

2.73KB

~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/test_Full_Adder_2_beh.prj

65B

~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/test_Full_Adder_2_stx_beh.prj

75B

~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/usage_statistics_webtalk.html

35.32KB

~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/webtalk.log

697B

~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/webtalk_pn.xml

3.13KB

~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/xilinxsim.ini

16B

~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/xlnx_auto_0_xdb/cst.xbcd

684B

~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/xst/work/hdllib.ref

232B

~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/xst/work/hdpdeps.ref

423B

~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/xst/work/sub00/vhpl00.vho

792B

~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/xst/work/sub00/vhpl01.vho

2.83KB

~Get Your Files Here !/03 - Pin Planning Tool/001 IO Pin Planning Tool Introduction.mp4

21.02MB

~Get Your Files Here !/03 - Pin Planning Tool/001 IO Pin Planning Tool Introduction_en.srt

2.56KB

~Get Your Files Here !/03 - Pin Planning Tool/002 Create an IO Pin Planning Project.mp4

7.22MB

~Get Your Files Here !/03 - Pin Planning Tool/002 Create an IO Pin Planning Project_en.srt

2.54KB

~Get Your Files Here !/03 - Pin Planning Tool/003 Create and Place IO Ports.mp4

16.03MB

~Get Your Files Here !/03 - Pin Planning Tool/003 Create and Place IO Ports_en.srt

5.49KB

~Get Your Files Here !/03 - Pin Planning Tool/004 Perform a Design Rules Check.mp4

6.27MB

~Get Your Files Here !/03 - Pin Planning Tool/004 Perform a Design Rules Check_en.srt

1.67KB

~Get Your Files Here !/03 - Pin Planning Tool/005 Report Simultaneous Switching Noise SSN.mp4

10.35MB

~Get Your Files Here !/03 - Pin Planning Tool/005 Report Simultaneous Switching Noise SSN_en.srt

4.46KB

~Get Your Files Here !/03 - Pin Planning Tool/006 Generate Contraints File and Top Level HDL File.mp4

14.66MB

~Get Your Files Here !/03 - Pin Planning Tool/006 Generate Contraints File and Top Level HDL File_en.srt

5.44KB

~Get Your Files Here !/03 - Pin Planning Tool/external-assets-links.txt

143B

~Get Your Files Here !/04 - Intellectual Property (IP) Cores/001 Introduction to IP Cores.html

9.28KB

~Get Your Files Here !/04 - Intellectual Property (IP) Cores/002 Using IP Cores.mp4

9MB

~Get Your Files Here !/04 - Intellectual Property (IP) Cores/002 Using IP Cores_en.srt

3.9KB

~Get Your Files Here !/04 - Intellectual Property (IP) Cores/003 Create IP Cores from a Specific Directory.mp4

20.18MB

~Get Your Files Here !/04 - Intellectual Property (IP) Cores/003 Create IP Cores from a Specific Directory_en.srt

9.35KB

~Get Your Files Here !/04 - Intellectual Property (IP) Cores/004 Create IP Cores from a Block Design.mp4

21.58MB

~Get Your Files Here !/04 - Intellectual Property (IP) Cores/004 Create IP Cores from a Block Design_en.srt

7.65KB

~Get Your Files Here !/04 - Intellectual Property (IP) Cores/005 AXI Interface Explained.html

15.28KB

~Get Your Files Here !/04 - Intellectual Property (IP) Cores/006 Create an AXI IP Core Peripheral Step 1.mp4

9.05MB

~Get Your Files Here !/04 - Intellectual Property (IP) Cores/006 Create an AXI IP Core Peripheral Step 1_en.srt

3.01KB

~Get Your Files Here !/04 - Intellectual Property (IP) Cores/007 Creating an AXI IP Core Peripheral - Step 2.html

24.6KB

~Get Your Files Here !/04 - Intellectual Property (IP) Cores/008 Create an AXI IP Core Peripheral Step 3.mp4

20.98MB

~Get Your Files Here !/04 - Intellectual Property (IP) Cores/008 Create an AXI IP Core Peripheral Step 3_en.srt

8.13KB

~Get Your Files Here !/04 - Intellectual Property (IP) Cores/009 Customizing IP Cores.mp4

10.04MB

~Get Your Files Here !/04 - Intellectual Property (IP) Cores/009 Customizing IP Cores_en.srt

2.89KB

~Get Your Files Here !/04 - Intellectual Property (IP) Cores/010 Creating a Custom IP Core Repository.html

1.11KB

~Get Your Files Here !/04 - Intellectual Property (IP) Cores/011 IP Core Repository Directory Structure.html

1.11KB

~Get Your Files Here !/04 - Intellectual Property (IP) Cores/012 Adding IP Cores to Your Repository.mp4

13.02MB

~Get Your Files Here !/04 - Intellectual Property (IP) Cores/012 Adding IP Cores to Your Repository_en.srt

4.34KB

~Get Your Files Here !/04 - Intellectual Property (IP) Cores/013 Adding a Custom IP Core Repository to a Vivado Project.mp4

6.23MB

~Get Your Files Here !/04 - Intellectual Property (IP) Cores/013 Adding a Custom IP Core Repository to a Vivado Project_en.srt

2.79KB

~Get Your Files Here !/04 - Intellectual Property (IP) Cores/014 Managing a Custom IP Core Repository.mp4

14.78MB

~Get Your Files Here !/04 - Intellectual Property (IP) Cores/014 Managing a Custom IP Core Repository_en.srt

5.45KB

~Get Your Files Here !/04 - Intellectual Property (IP) Cores/BASYS_7_seg/BASYS_7_seg.vhd

3.48KB

~Get Your Files Here !/04 - Intellectual Property (IP) Cores/BASYS_7_seg/BASYS_7_seg_documentation.pdf

560.18KB

~Get Your Files Here !/04 - Intellectual Property (IP) Cores/BASYS_7_seg_AXI_1.0/bd/bd.tcl

7.65KB

~Get Your Files Here !/04 - Intellectual Property (IP) Cores/BASYS_7_seg_AXI_1.0/component.xml

39.63KB

~Get Your Files Here !/04 - Intellectual Property (IP) Cores/BASYS_7_seg_AXI_1.0/drivers/BASYS_7_seg_AXI_v1_0/data/BASYS_7_seg_AXI.mdd

210B

~Get Your Files Here !/04 - Intellectual Property (IP) Cores/BASYS_7_seg_AXI_1.0/drivers/BASYS_7_seg_AXI_v1_0/data/BASYS_7_seg_AXI.tcl

177B

~Get Your Files Here !/04 - Intellectual Property (IP) Cores/BASYS_7_seg_AXI_1.0/drivers/BASYS_7_seg_AXI_v1_0/src/BASYS_7_seg_AXI.c

194B

~Get Your Files Here !/04 - Intellectual Property (IP) Cores/BASYS_7_seg_AXI_1.0/drivers/BASYS_7_seg_AXI_v1_0/src/BASYS_7_seg_AXI.h

2.59KB

~Get Your Files Here !/04 - Intellectual Property (IP) Cores/BASYS_7_seg_AXI_1.0/drivers/BASYS_7_seg_AXI_v1_0/src/BASYS_7_seg_AXI_selftest.c

1.99KB

~Get Your Files Here !/04 - Intellectual Property (IP) Cores/BASYS_7_seg_AXI_1.0/drivers/BASYS_7_seg_AXI_v1_0/src/Makefile

484B

~Get Your Files Here !/04 - Intellectual Property (IP) Cores/BASYS_7_seg_AXI_1.0/example_designs/bfm_design/BASYS_7_seg_AXI_v1_0_tb.v

6.84KB

~Get Your Files Here !/04 - Intellectual Property (IP) Cores/BASYS_7_seg_AXI_1.0/example_designs/bfm_design/design.tcl

3.84KB

~Get Your Files Here !/04 - Intellectual Property (IP) Cores/BASYS_7_seg_AXI_1.0/example_designs/debug_hw_design/BASYS_7_seg_AXI_v1_0_hw_test.tcl

1.38KB

~Get Your Files Here !/04 - Intellectual Property (IP) Cores/BASYS_7_seg_AXI_1.0/example_designs/debug_hw_design/design.tcl

8.34KB

~Get Your Files Here !/04 - Intellectual Property (IP) Cores/BASYS_7_seg_AXI_1.0/hdl/BASYS_7_seg_AXI_v1_0.vhd

4.29KB

~Get Your Files Here !/04 - Intellectual Property (IP) Cores/BASYS_7_seg_AXI_1.0/hdl/BASYS_7_seg_AXI_v1_0_S00_AXI.vhd

17KB

~Get Your Files Here !/04 - Intellectual Property (IP) Cores/BASYS_7_seg_AXI_1.0/src/BASYS_7_seg.vhd

3.48KB

~Get Your Files Here !/04 - Intellectual Property (IP) Cores/BASYS_7_seg_AXI_1.0/xgui/BASYS_7_seg_AXI_v1_0.tcl

4.04KB

~Get Your Files Here !/04 - Intellectual Property (IP) Cores/Custom_IP_Cores/BASYS_7_seg/BASYS_7_seg.vhd

3.48KB

~Get Your Files Here !/04 - Intellectual Property (IP) Cores/Custom_IP_Cores/BASYS_7_seg/component.xml

14.15KB

~Get Your Files Here !/04 - Intellectual Property (IP) Cores/Custom_IP_Cores/BASYS_7_seg/doc/BASYS_7_seg_documentation.pdf

560.18KB

~Get Your Files Here !/04 - Intellectual Property (IP) Cores/Custom_IP_Cores/BASYS_7_seg/src/basys_image.PNG

9.92KB

~Get Your Files Here !/04 - Intellectual Property (IP) Cores/Custom_IP_Cores/BASYS_7_seg/xgui/BASYS_7_seg_v1_0.tcl

1.59KB

~Get Your Files Here !/04 - Intellectual Property (IP) Cores/Custom_IP_Cores/BASYS_7_seg_AXI_1.0/bd/bd.tcl

7.65KB

~Get Your Files Here !/04 - Intellectual Property (IP) Cores/Custom_IP_Cores/BASYS_7_seg_AXI_1.0/component.xml

39.63KB

~Get Your Files Here !/04 - Intellectual Property (IP) Cores/Custom_IP_Cores/BASYS_7_seg_AXI_1.0/drivers/BASYS_7_seg_AXI_v1_0/data/BASYS_7_seg_AXI.mdd

210B

~Get Your Files Here !/04 - Intellectual Property (IP) Cores/Custom_IP_Cores/BASYS_7_seg_AXI_1.0/drivers/BASYS_7_seg_AXI_v1_0/data/BASYS_7_seg_AXI.tcl

177B

~Get Your Files Here !/04 - Intellectual Property (IP) Cores/Custom_IP_Cores/BASYS_7_seg_AXI_1.0/drivers/BASYS_7_seg_AXI_v1_0/src/BASYS_7_seg_AXI.c

194B

~Get Your Files Here !/04 - Intellectual Property (IP) Cores/Custom_IP_Cores/BASYS_7_seg_AXI_1.0/drivers/BASYS_7_seg_AXI_v1_0/src/BASYS_7_seg_AXI.h

2.59KB

~Get Your Files Here !/04 - Intellectual Property (IP) Cores/Custom_IP_Cores/BASYS_7_seg_AXI_1.0/drivers/BASYS_7_seg_AXI_v1_0/src/BASYS_7_seg_AXI_selftest.c

1.99KB

~Get Your Files Here !/04 - Intellectual Property (IP) Cores/Custom_IP_Cores/BASYS_7_seg_AXI_1.0/drivers/BASYS_7_seg_AXI_v1_0/src/Makefile

484B

~Get Your Files Here !/04 - Intellectual Property (IP) Cores/Custom_IP_Cores/BASYS_7_seg_AXI_1.0/example_designs/bfm_design/BASYS_7_seg_AXI_v1_0_tb.v

6.84KB

~Get Your Files Here !/04 - Intellectual Property (IP) Cores/Custom_IP_Cores/BASYS_7_seg_AXI_1.0/example_designs/bfm_design/design.tcl

3.84KB

~Get Your Files Here !/04 - Intellectual Property (IP) Cores/Custom_IP_Cores/BASYS_7_seg_AXI_1.0/example_designs/debug_hw_design/BASYS_7_seg_AXI_v1_0_hw_test.tcl

1.38KB

~Get Your Files Here !/04 - Intellectual Property (IP) Cores/Custom_IP_Cores/BASYS_7_seg_AXI_1.0/example_designs/debug_hw_design/design.tcl

8.34KB

~Get Your Files Here !/04 - Intellectual Property (IP) Cores/Custom_IP_Cores/BASYS_7_seg_AXI_1.0/hdl/BASYS_7_seg_AXI_v1_0.vhd

4.29KB

~Get Your Files Here !/04 - Intellectual Property (IP) Cores/Custom_IP_Cores/BASYS_7_seg_AXI_1.0/hdl/BASYS_7_seg_AXI_v1_0_S00_AXI.vhd

17KB

~Get Your Files Here !/04 - Intellectual Property (IP) Cores/Custom_IP_Cores/BASYS_7_seg_AXI_1.0/src/BASYS_7_seg.vhd

3.48KB

~Get Your Files Here !/04 - Intellectual Property (IP) Cores/Custom_IP_Cores/BASYS_7_seg_AXI_1.0/xgui/BASYS_7_seg_AXI_v1_0.tcl

4.04KB

~Get Your Files Here !/04 - Intellectual Property (IP) Cores/Custom_IP_Cores/design_1/component.xml

11.79KB

~Get Your Files Here !/04 - Intellectual Property (IP) Cores/Custom_IP_Cores/design_1/src/design_1.hwdef

4.27KB

~Get Your Files Here !/04 - Intellectual Property (IP) Cores/Custom_IP_Cores/design_1/src/design_1.vhd

2.17KB

~Get Your Files Here !/04 - Intellectual Property (IP) Cores/Custom_IP_Cores/design_1/src/design_1_c_counter_binary_0_0/design_1_c_counter_binary_0_0.xci

10.35KB

~Get Your Files Here !/04 - Intellectual Property (IP) Cores/Custom_IP_Cores/design_1/src/design_1_c_counter_binary_1_0/design_1_c_counter_binary_1_0.xci

10.35KB

~Get Your Files Here !/04 - Intellectual Property (IP) Cores/Custom_IP_Cores/design_1/src/design_1_ooc.xdc

600B

~Get Your Files Here !/04 - Intellectual Property (IP) Cores/Custom_IP_Cores/design_1/xgui/design_1_v1_0.tcl

205B

~Get Your Files Here !/04 - Intellectual Property (IP) Cores/external-assets-links.txt

324B

~Get Your Files Here !/05 - IP Core Design Examples/001 Configure Internal FPGA Block RAM (BRAM).mp4

13.77MB

~Get Your Files Here !/05 - IP Core Design Examples/001 Configure Internal FPGA Block RAM (BRAM)_en.srt

5.39KB

~Get Your Files Here !/05 - IP Core Design Examples/002 Xilinx Memory Interface Generator (MIG) IP Core.mp4

21.86MB

~Get Your Files Here !/05 - IP Core Design Examples/002 Xilinx Memory Interface Generator (MIG) IP Core_en.srt

8.56KB

~Get Your Files Here !/05 - IP Core Design Examples/003 Connecting Multiple AXI Peripherals to a Single Master.mp4

9.87MB

~Get Your Files Here !/05 - IP Core Design Examples/003 Connecting Multiple AXI Peripherals to a Single Master_en.srt

3.05KB

~Get Your Files Here !/05 - IP Core Design Examples/004 Using Vivado's Connection Automation and Regerating Block Design Layouts.mp4

12.45MB

~Get Your Files Here !/05 - IP Core Design Examples/004 Using Vivado's Connection Automation and Regerating Block Design Layouts_en.srt

4.27KB

~Get Your Files Here !/05 - IP Core Design Examples/BRAM_Init_File/memory_init.coe

1.06KB

~Get Your Files Here !/05 - IP Core Design Examples/external-assets-links.txt

95B

~Get Your Files Here !/06 - Working with Design Constraints/001 What are Design Constraints.html

2.04KB

~Get Your Files Here !/06 - Working with Design Constraints/002 Applying IO Constraints.mp4

10.09MB

~Get Your Files Here !/06 - Working with Design Constraints/002 Applying IO Constraints_en.srt

3.57KB

~Get Your Files Here !/06 - Working with Design Constraints/003 Creating Clock Constraints.mp4

11.32MB

~Get Your Files Here !/06 - Working with Design Constraints/003 Creating Clock Constraints_en.srt

4.02KB

~Get Your Files Here !/06 - Working with Design Constraints/external-assets-links.txt

313B

~Get Your Files Here !/07 - Automating Vivado/001 TCL Script Introduction.mp4

31.08MB

~Get Your Files Here !/07 - Automating Vivado/001 TCL Script Introduction_en.srt

4.12KB

~Get Your Files Here !/07 - Automating Vivado/002 Build a Vivado Project Using TCL Scripts.mp4

10.47MB

~Get Your Files Here !/07 - Automating Vivado/002 Build a Vivado Project Using TCL Scripts_en.srt

4.12KB

~Get Your Files Here !/07 - Automating Vivado/003 Populate a Block Design Using TCL Scripts.mp4

4.89MB

~Get Your Files Here !/07 - Automating Vivado/003 Populate a Block Design Using TCL Scripts_en.srt

1.46KB

~Get Your Files Here !/07 - Automating Vivado/004 Using TCL Scripts in Your Custom IP Core.mp4

10.76MB

~Get Your Files Here !/07 - Automating Vivado/004 Using TCL Scripts in Your Custom IP Core_en.srt

3.99KB

~Get Your Files Here !/07 - Automating Vivado/005 How to Create Your Own Custom TCL Scripts.mp4

11.18MB

~Get Your Files Here !/07 - Automating Vivado/005 How to Create Your Own Custom TCL Scripts_en.srt

4.68KB

~Get Your Files Here !/07 - Automating Vivado/GPIO/proj/_READ_ME_.txt

670B

~Get Your Files Here !/07 - Automating Vivado/GPIO/proj/cleanup.cmd

453B

~Get Your Files Here !/07 - Automating Vivado/GPIO/proj/cleanup.sh

533B

~Get Your Files Here !/07 - Automating Vivado/GPIO/proj/create_project.tcl

3.7KB

~Get Your Files Here !/07 - Automating Vivado/GPIO/src/constraints/Basys3_Master.xdc

16.06KB

~Get Your Files Here !/07 - Automating Vivado/GPIO/src/hdl/GPIO_Demo.vhd

16.02KB

~Get Your Files Here !/07 - Automating Vivado/GPIO/src/hdl/MouseCtl.vhd

47.67KB

~Get Your Files Here !/07 - Automating Vivado/GPIO/src/hdl/MouseDisplay.vhd

11.61KB

~Get Your Files Here !/07 - Automating Vivado/GPIO/src/hdl/Ps2Interface.vhd

31.34KB

~Get Your Files Here !/07 - Automating Vivado/GPIO/src/hdl/UART_TX_CTRL.vhd

4.48KB

~Get Your Files Here !/07 - Automating Vivado/GPIO/src/hdl/clk_wiz_0.vhd

4.24KB

~Get Your Files Here !/07 - Automating Vivado/GPIO/src/hdl/clk_wiz_0_clk_wiz.vhd

7.06KB

~Get Your Files Here !/07 - Automating Vivado/GPIO/src/hdl/debouncer.vhd

3.33KB

~Get Your Files Here !/07 - Automating Vivado/GPIO/src/hdl/vga_ctrl.vhd

14.06KB

~Get Your Files Here !/07 - Automating Vivado/design_1_tcl/design_1.tcl

6.58KB

~Get Your Files Here !/07 - Automating Vivado/external-assets-links.txt

177B

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/001 Creating Simulation Files (Test Benches).html

6.76KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/002 Simulating Your Designs in Vivado.mp4

13.25MB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/002 Simulating Your Designs in Vivado_en.srt

4.71KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/003 Modifying the Simulation Waveform.mp4

19.91MB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/003 Modifying the Simulation Waveform_en.srt

9.09KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/004 Forcing Signal Values for Simulation.mp4

11.1MB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/004 Forcing Signal Values for Simulation_en.srt

4.74KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/005 Vivado Debugging Tools Introduction.mp4

30.6MB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/005 Vivado Debugging Tools Introduction_en.srt

3.62KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/006 How to Use the Integrated Logic Analyzer (ILA) Core for Debugging.mp4

26.98MB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/006 How to Use the Integrated Logic Analyzer (ILA) Core for Debugging_en.srt

11.29KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/007 How to Use the Virtual IO (VIO) Core for Debugging.mp4

23.4MB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/007 How to Use the Virtual IO (VIO) Core for Debugging_en.srt

9.61KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.cache/ip/46a4281943398b66/46a4281943398b66.xci

6.07KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.cache/ip/46a4281943398b66/dbg_hub_CV.dcp

221.19KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.cache/wt/java_command_handlers.wdf

417B

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.cache/wt/project.wpc

121B

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.cache/wt/synthesis.wdf

3.67KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.cache/wt/synthesis_details.wdf

100B

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.cache/wt/webtalk_pa.xml

1.51KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.cache/wt/xsim.wdf

256B

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.hw/Simulation_Example.lpr

343B

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.hw/hw_1/hw.xml

8KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.hw/hw_1/layout/hw_ila_1.layout

241.54KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.hw/hw_1/wave/hw_ila_data_1/hw_ila_data_1.wcfg

1.4KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.hw/hw_1/wave/hw_ila_data_1/hw_ila_data_1.wdb

16.04KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.hw/webtalk/labtool_webtalk.log

386B

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.hw/webtalk/usage_statistics_ext_labtool.html

10.29KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.hw/webtalk/usage_statistics_ext_labtool.xml

10.04KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.hw/webtalk/xsim_webtallk.info

59B

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.ip_user_files/README.txt

130B

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.ip_user_files/bd/design_1/hdl/design_1.vhd

6.8KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.ip_user_files/bd/design_1/ip/design_1_BASYS_7_seg_0_0/sim/design_1_BASYS_7_seg_0_0.vhd

3.94KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.ip_user_files/bd/design_1/ip/design_1_Hex_to_7_Seg_0_0/sim/design_1_Hex_to_7_Seg_0_0.vhd

3.02KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.ip_user_files/bd/design_1/ip/design_1_Hex_to_7_Seg_1_0/sim/design_1_Hex_to_7_Seg_1_0.vhd

3.02KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.ip_user_files/bd/design_1/ip/design_1_Hex_to_7_Seg_2_0/sim/design_1_Hex_to_7_Seg_2_0.vhd

3.02KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.ip_user_files/bd/design_1/ip/design_1_Hex_to_7_Seg_3_0/sim/design_1_Hex_to_7_Seg_3_0.vhd

3.02KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.ip_user_files/bd/design_1/ip/design_1_c_counter_binary_0_0/sim/design_1_c_counter_binary_0_0.vhd

5.05KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.ip_user_files/bd/design_1/ip/design_1_xlslice_0_0/sim/design_1_xlslice_0_0.vhd

3.16KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.ip_user_files/bd/design_1/ip/design_1_xlslice_1_0/sim/design_1_xlslice_1_0.vhd

3.16KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.ip_user_files/bd/design_1/ip/design_1_xlslice_2_0/sim/design_1_xlslice_2_0.vhd

3.16KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.ip_user_files/bd/design_1/ip/design_1_xlslice_3_0/sim/design_1_xlslice_3_0.vhd

3.16KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.ip_user_files/bd/design_1/ipshared/xilinx.com/basys_7_seg_v1_0/BASYS_7_seg.vhd

3.48KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.ip_user_files/bd/design_1/ipshared/xilinx.com/hex_to_7_seg_v1_0/Hex_to_7_Seg.vhd

1.1KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.ip_user_files/bd/design_1/ipshared/xilinx.com/xlslice_v1_0/xlslice.vhd

1.2KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.ip_user_files/ipstatic/c_addsub_v12_0/hdl/c_addsub_v12_0.vhd

12.29KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.ip_user_files/ipstatic/c_addsub_v12_0/hdl/c_addsub_v12_0_vh_rfs.vhd

383.7KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.ip_user_files/ipstatic/c_counter_binary_v12_0/hdl/c_counter_binary_v12_0.vhd

10.6KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.ip_user_files/ipstatic/c_counter_binary_v12_0/hdl/c_counter_binary_v12_0_vh_rfs.vhd

125.74KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.ip_user_files/ipstatic/c_gate_bit_v12_0/hdl/c_gate_bit_v12_0.vhd

10.72KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.ip_user_files/ipstatic/c_gate_bit_v12_0/hdl/c_gate_bit_v12_0_vh_rfs.vhd

155.7KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.ip_user_files/ipstatic/c_reg_fd_v12_0/hdl/c_reg_fd_v12_0.vhd

8.91KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.ip_user_files/ipstatic/c_reg_fd_v12_0/hdl/c_reg_fd_v12_0_vh_rfs.vhd

31.94KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.ip_user_files/ipstatic/xbip_addsub_v3_0/hdl/xbip_addsub_v3_0.vhd

9.36KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.ip_user_files/ipstatic/xbip_addsub_v3_0/hdl/xbip_addsub_v3_0_vh_rfs.vhd

26.58KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.ip_user_files/ipstatic/xbip_counter_v3_0/hdl/xbip_counter_v3_0.vhd

9.56KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.ip_user_files/ipstatic/xbip_counter_v3_0/hdl/xbip_counter_v3_0_vh_rfs.vhd

127.52KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.ip_user_files/ipstatic/xbip_dsp48_addsub_v3_0/hdl/xbip_dsp48_addsub_v3_0.vhd

10.56KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.ip_user_files/ipstatic/xbip_dsp48_addsub_v3_0/hdl/xbip_dsp48_addsub_v3_0_vh_rfs.vhd

84.71KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.ip_user_files/ipstatic/xbip_dsp48_wrapper_v3_0/hdl/xbip_dsp48_wrapper_v3_0_vh_rfs.vhd

139.27KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.ip_user_files/ipstatic/xbip_pipe_v3_0/hdl/xbip_pipe_v3_0.vhd

8.13KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.ip_user_files/ipstatic/xbip_pipe_v3_0/hdl/xbip_pipe_v3_0_vh_rfs.vhd

24.07KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.ip_user_files/ipstatic/xbip_utils_v3_0/hdl/xbip_utils_v3_0_vh_rfs.vhd

154.09KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.runs/impl_1/ISEWrap.js

7.14KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.runs/impl_1/ISEWrap.sh

1.58KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.runs/impl_1/Vivado_Implementation.queue.rst

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.runs/impl_1/debug_nets.ltx

2.62KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.runs/impl_1/design_1_wrapper.bit

2.09MB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.runs/impl_1/design_1_wrapper.hwdef

25.06KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.runs/impl_1/design_1_wrapper.sysdef

75.46KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.runs/impl_1/design_1_wrapper.tcl

1.9KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.runs/impl_1/design_1_wrapper.vdi

26.57KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.runs/impl_1/design_1_wrapper_10904.backup.vdi

22.14KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.runs/impl_1/design_1_wrapper_11256.backup.vdi

22.09KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.runs/impl_1/design_1_wrapper_20632.backup.vdi

21.2KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.runs/impl_1/design_1_wrapper_clock_utilization_routed.rpt

9.2KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.runs/impl_1/design_1_wrapper_control_sets_placed.rpt

53.91KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.runs/impl_1/design_1_wrapper_drc_opted.rpt

1.6KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.runs/impl_1/design_1_wrapper_drc_routed.pb

37B

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.runs/impl_1/design_1_wrapper_drc_routed.rpt

4.06KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.runs/impl_1/design_1_wrapper_io_placed.rpt

60.07KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.runs/impl_1/design_1_wrapper_opt.dcp

918.46KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.runs/impl_1/design_1_wrapper_placed.dcp

1.13MB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.runs/impl_1/design_1_wrapper_power_routed.rpt

30.65KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.runs/impl_1/design_1_wrapper_power_summary_routed.pb

674B

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.runs/impl_1/design_1_wrapper_route_status.pb

44B

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.runs/impl_1/design_1_wrapper_route_status.rpt

651B

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1.29MB

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352.2KB

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731.43KB

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249B

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6.18KB

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401B

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177B

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177B

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177B

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21.93KB

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3.83KB

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177B

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10.41KB

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1.37KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.runs/impl_1/runme.bat

229B

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26.38KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.runs/impl_1/runme.sh

1.24KB

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197.42KB

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301.91KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.runs/impl_1/vivado.begin.rst

352B

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149B

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.runs/impl_1/vivado_10904.backup.jou

769B

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769B

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769B

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177B

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6.16KB

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230B

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251B

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230B

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251B

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230B

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7.14KB

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1.58KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.runs/synth_1/Vivado_Synthesis.queue.rst

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.runs/synth_1/Xil/design_1_wrapper_propImpl.xdc

2.87KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.runs/synth_1/design_1_wrapper.dcp

580.87KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.runs/synth_1/design_1_wrapper.tcl

2.68KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.runs/synth_1/design_1_wrapper.vds

206.29KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.runs/synth_1/design_1_wrapper_utilization_synth.pb

249B

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.runs/synth_1/design_1_wrapper_utilization_synth.rpt

7.59KB

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2.93KB

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2.78KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.runs/synth_1/htr.txt

393B

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.runs/synth_1/project.wdf

3.83KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.runs/synth_1/rundef.js

1.29KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.runs/synth_1/runme.bat

229B

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.runs/synth_1/runme.log

207.08KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.runs/synth_1/runme.sh

1.18KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.runs/synth_1/vivado.begin.rst

175B

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~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.runs/synth_1/vivado.jou

764B

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.runs/synth_1/vivado.pb

302.43KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/Simulation_Example_sim.tcl

458B

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7.16MB

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4.35KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/compile.bat

345B

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9.53KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/elaborate.bat

615B

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4.72KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/simulate.bat

321B

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/simulate.log

50B

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943B

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1012B

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/webtalk_19988.backup.jou

944B

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/webtalk_19988.backup.log

1013B

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xelab.pb

8.19KB

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467B

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29B

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/Simulation_Example_sim_behav/webtalk/usage_statistics_ext_xsim.html

3.17KB

2.75KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/Simulation_Example_sim_behav/webtalk/xsim_webtallk.info

64B

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/Simulation_Example_sim_behav/xsim.dbg

17.57KB

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14.05KB

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8.36KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/Simulation_Example_sim_behav/xsim.rtti

332B

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~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/Simulation_Example_sim_behav/xsim.type

9.02KB

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7.92KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/Simulation_Example_sim_behav/xsimcrash.log

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/Simulation_Example_sim_behav/xsimk.exe

187.02KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/Simulation_Example_sim_behav/xsimkernel.log

360B

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/c_addsub_v12_0_8/c_addsub_v12_0_8.vdb

8.32KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/c_addsub_v12_0_8/c_addsub_v12_0_8_base_legacy.vdb

70.59KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/c_addsub_v12_0_8/c_addsub_v12_0_8_comp.vdb

5.45KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/c_addsub_v12_0_8/c_addsub_v12_0_8_fabric_legacy.vdb

13.71KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/c_addsub_v12_0_8/c_addsub_v12_0_8_legacy.vdb

58.96KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/c_addsub_v12_0_8/c_addsub_v12_0_8_lut6_legacy.vdb

69.48KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/c_addsub_v12_0_8/c_addsub_v12_0_8_pkg.vdb

48.95KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/c_addsub_v12_0_8/c_addsub_v12_0_8_pkg_legacy.vdb

68.71KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/c_addsub_v12_0_8/c_addsub_v12_0_8_viv.vdb

41.46KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/c_addsub_v12_0_8/c_addsub_v12_0_8_viv_comp.vdb

5.48KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/c_counter_binary_v12_0_8/c_counter_binary_v12_0_8.vdb

7.28KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/c_counter_binary_v12_0_8/c_counter_binary_v12_0_8_comp.vdb

4.7KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/c_counter_binary_v12_0_8/c_counter_binary_v12_0_8_legacy.vdb

56.2KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/c_counter_binary_v12_0_8/c_counter_binary_v12_0_8_pkg.vdb

43KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/c_counter_binary_v12_0_8/c_counter_binary_v12_0_8_viv.vdb

16.79KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/c_counter_binary_v12_0_8/c_counter_binary_v12_0_8_viv_comp.vdb

4.71KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/c_gate_bit_v12_0_1/c_gate_bit_tier.vdb

4.96KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/c_gate_bit_v12_0_1/c_gate_bit_tile.vdb

15.7KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/c_gate_bit_v12_0_1/c_gate_bit_v12_0_1.vdb

7.26KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/c_gate_bit_v12_0_1/c_gate_bit_v12_0_1_comp.vdb

4.46KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/c_gate_bit_v12_0_1/c_gate_bit_v12_0_1_viv.vdb

37.28KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/c_gate_bit_v12_0_1/c_gate_bit_v12_0_1_viv_comp.vdb

4.5KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/c_gate_bit_v12_0_1/pkg_gate_bit_v12_0.vdb

120.03KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/c_reg_fd_v12_0_1/c_reg_fd_v12_0_1.vdb

5.42KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/c_reg_fd_v12_0_1/c_reg_fd_v12_0_1_comp.vdb

3.67KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/c_reg_fd_v12_0_1/c_reg_fd_v12_0_1_viv.vdb

17.48KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/c_reg_fd_v12_0_1/c_reg_fd_v12_0_1_viv_comp.vdb

3.7KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/xbip_addsub_v3_0_1/xbip_addsub_v3_0_1.vdb

5.21KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/xbip_addsub_v3_0_1/xbip_addsub_v3_0_1_comp.vdb

3.46KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/xbip_addsub_v3_0_1/xbip_addsub_v3_0_1_viv.vdb

11.68KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/xbip_addsub_v3_0_1/xbip_addsub_v3_0_1_viv_comp.vdb

3.5KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/xbip_counter_v3_0_1/dsp48_counter.vdb

15.21KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/xbip_counter_v3_0_1/fabric_counter.vdb

24.65KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/xbip_counter_v3_0_1/xbip_counter_v3_0_1.vdb

6.03KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/xbip_counter_v3_0_1/xbip_counter_v3_0_1_comp.vdb

3.89KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/xbip_counter_v3_0_1/xbip_counter_v3_0_1_hdl_comps.vdb

6.23KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/xbip_counter_v3_0_1/xbip_counter_v3_0_1_pkg.vdb

54.11KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/xbip_counter_v3_0_1/xbip_counter_v3_0_1_viv.vdb

32.17KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/xbip_counter_v3_0_1/xbip_counter_v3_0_1_viv_comp.vdb

3.92KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/xbip_dsp48_addsub_v3_0_1/xbip_dsp48_addsub_rtl.vdb

24.54KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/xbip_dsp48_addsub_v3_0_1/xbip_dsp48_addsub_synth.vdb

12.87KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/xbip_dsp48_addsub_v3_0_1/xbip_dsp48_addsub_v3_0_1.vdb

7.43KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/xbip_dsp48_addsub_v3_0_1/xbip_dsp48_addsub_v3_0_1_comp.vdb

5.7KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/xbip_dsp48_addsub_v3_0_1/xbip_dsp48_addsub_v3_0_1_pkg.vdb

30.18KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/xbip_dsp48_addsub_v3_0_1/xbip_dsp48_addsub_v3_0_1_viv.vdb

10.45KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/xbip_dsp48_addsub_v3_0_1/xbip_dsp48_addsub_v3_0_1_viv_comp.vdb

5.73KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/xbip_dsp48_wrapper_v3_0_4/xbip_dsp48_wrapper_v3_0_4.vdb

19.54KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/xbip_dsp48_wrapper_v3_0_4/xbip_dsp48_wrapper_v3_0_4_pkg.vdb

34.26KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/xbip_dsp48_wrapper_v3_0_4/xbip_dsp48a1_wrapper_v3_0.vdb

19.93KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/xbip_dsp48_wrapper_v3_0_4/xbip_dsp48a_wrapper_v3_0.vdb

19.06KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/xbip_dsp48_wrapper_v3_0_4/xbip_dsp48e1_wrapper_v3_0.vdb

27.86KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/xbip_dsp48_wrapper_v3_0_4/xbip_dsp48e2_wrapper_v3_0.vdb

29.25KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/xbip_dsp48_wrapper_v3_0_4/xbip_dsp48e_wrapper_v3_0.vdb

25.39KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/xbip_pipe_v3_0_1/xbip_pipe_v3_0_1.vdb

4.92KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/xbip_pipe_v3_0_1/xbip_pipe_v3_0_1_comp.vdb

3.17KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/xbip_pipe_v3_0_1/xbip_pipe_v3_0_1_viv.vdb

14.93KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/xbip_pipe_v3_0_1/xbip_pipe_v3_0_1_viv_comp.vdb

3.18KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/xbip_utils_v3_0_5/xbip_utils_v3_0_5_pkg.vdb

214.53KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/xbip_utils_v3_0_5/xcc_utils_v3_0.vdb

2.26KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/xil_defaultlib/basys_7_seg.vdb

5.32KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/xil_defaultlib/design_1.vdb

16.75KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/xil_defaultlib/design_1_basys_7_seg_0_0.vdb

4.99KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/xil_defaultlib/design_1_c_counter_binary_0_0.vdb

7.35KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/xil_defaultlib/design_1_hex_to_7_seg_0_0.vdb

2.31KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/xil_defaultlib/design_1_hex_to_7_seg_1_0.vdb

2.31KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/xil_defaultlib/design_1_hex_to_7_seg_2_0.vdb

2.31KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/xil_defaultlib/design_1_hex_to_7_seg_3_0.vdb

2.31KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/xil_defaultlib/design_1_wrapper.vdb

3.34KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/xil_defaultlib/design_1_xlslice_0_0.vdb

2.72KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/xil_defaultlib/design_1_xlslice_1_0.vdb

2.72KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/xil_defaultlib/design_1_xlslice_2_0.vdb

2.72KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/xil_defaultlib/design_1_xlslice_3_0.vdb

2.72KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/xil_defaultlib/hex_to_7_seg.vdb

3.19KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/xil_defaultlib/simulation_example_sim.vdb

3.76KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/xil_defaultlib/xlslice.vdb

1.85KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xvhdl.log

9.53KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xvhdl.pb

14.15KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/constrs_1/imports/XDC/Basys3_Master.xdc

13.13KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sim_1/imports/Lecture_Example/Simulation_Example_sim.vhd

1.66KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/design_1.bd

23.44KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/design_1.bxml

6.34KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/design_1_ooc.xdc

600B

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/hdl/design_1.hwdef

25.01KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/hdl/design_1.vhd

7.27KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/hdl/design_1_wrapper.vhd

1.45KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/hw_handoff/design_1.hwh

236.38KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/hw_handoff/design_1_bd.tcl

11.95KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ip/design_1_BASYS_7_seg_0_0/design_1_BASYS_7_seg_0_0.veo

3.2KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ip/design_1_BASYS_7_seg_0_0/design_1_BASYS_7_seg_0_0.vho

3.52KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ip/design_1_BASYS_7_seg_0_0/design_1_BASYS_7_seg_0_0.xci

4.68KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ip/design_1_BASYS_7_seg_0_0/design_1_BASYS_7_seg_0_0.xml

20.29KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ip/design_1_BASYS_7_seg_0_0/sim/design_1_BASYS_7_seg_0_0.vhd

3.94KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ip/design_1_BASYS_7_seg_0_0/synth/design_1_BASYS_7_seg_0_0.vhd

4.6KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ip/design_1_Hex_to_7_Seg_0_0/design_1_Hex_to_7_Seg_0_0.veo

2.93KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ip/design_1_Hex_to_7_Seg_0_0/design_1_Hex_to_7_Seg_0_0.vho

3.16KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ip/design_1_Hex_to_7_Seg_0_0/design_1_Hex_to_7_Seg_0_0.xci

3.22KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ip/design_1_Hex_to_7_Seg_0_0/design_1_Hex_to_7_Seg_0_0.xml

12.25KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ip/design_1_Hex_to_7_Seg_0_0/sim/design_1_Hex_to_7_Seg_0_0.vhd

3.02KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ip/design_1_Hex_to_7_Seg_0_0/synth/design_1_Hex_to_7_Seg_0_0.vhd

3.64KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ip/design_1_Hex_to_7_Seg_1_0/design_1_Hex_to_7_Seg_1_0.veo

2.93KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ip/design_1_Hex_to_7_Seg_1_0/design_1_Hex_to_7_Seg_1_0.vho

3.16KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ip/design_1_Hex_to_7_Seg_1_0/design_1_Hex_to_7_Seg_1_0.xci

3.22KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ip/design_1_Hex_to_7_Seg_1_0/design_1_Hex_to_7_Seg_1_0.xml

12.25KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ip/design_1_Hex_to_7_Seg_1_0/sim/design_1_Hex_to_7_Seg_1_0.vhd

3.02KB

3.64KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ip/design_1_Hex_to_7_Seg_2_0/design_1_Hex_to_7_Seg_2_0.veo

2.93KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ip/design_1_Hex_to_7_Seg_2_0/design_1_Hex_to_7_Seg_2_0.vho

3.16KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ip/design_1_Hex_to_7_Seg_2_0/design_1_Hex_to_7_Seg_2_0.xci

3.22KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ip/design_1_Hex_to_7_Seg_2_0/design_1_Hex_to_7_Seg_2_0.xml

12.25KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ip/design_1_Hex_to_7_Seg_2_0/sim/design_1_Hex_to_7_Seg_2_0.vhd

3.02KB

3.64KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ip/design_1_Hex_to_7_Seg_3_0/design_1_Hex_to_7_Seg_3_0.veo

2.93KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ip/design_1_Hex_to_7_Seg_3_0/design_1_Hex_to_7_Seg_3_0.vho

3.16KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ip/design_1_Hex_to_7_Seg_3_0/design_1_Hex_to_7_Seg_3_0.xci

3.22KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ip/design_1_Hex_to_7_Seg_3_0/design_1_Hex_to_7_Seg_3_0.xml

12.25KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ip/design_1_Hex_to_7_Seg_3_0/sim/design_1_Hex_to_7_Seg_3_0.vhd

3.02KB

3.64KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ip/design_1_c_counter_binary_0_0/design_1_c_counter_binary_0_0.veo

2.95KB

3.18KB

10.66KB

77.08KB

2.44KB

4.88KB

5.05KB

6.07KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ip/design_1_ila_0_0/design_1_ila_0_0.vho

3.08KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ip/design_1_ila_0_0/design_1_ila_0_0.xci

447.68KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ip/design_1_ila_0_0/design_1_ila_0_0.xml

4.53MB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ip/design_1_ila_0_0/design_1_ila_0_0_ooc.xdc

2.44KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ip/design_1_ila_0_0/doc/ila_v6_0_changelog.txt

4.34KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ip/design_1_ila_0_0/ila_v6_0/constraints/ila.xdc

13.78KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ip/design_1_ila_0_0/sim/design_1_ila_0_0.vhd

2.56KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ip/design_1_ila_0_0/synth/design_1_ila_0_0.vhd

409.27KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ip/design_1_xlslice_0_0/design_1_xlslice_0_0.veo

2.89KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ip/design_1_xlslice_0_0/design_1_xlslice_0_0.vho

3.12KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ip/design_1_xlslice_0_0/design_1_xlslice_0_0.xci

4.68KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ip/design_1_xlslice_0_0/design_1_xlslice_0_0.xml

15.2KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ip/design_1_xlslice_0_0/sim/design_1_xlslice_0_0.vhd

3.16KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ip/design_1_xlslice_0_0/synth/design_1_xlslice_0_0.vhd

3.78KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ip/design_1_xlslice_1_0/design_1_xlslice_1_0.veo

2.89KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ip/design_1_xlslice_1_0/design_1_xlslice_1_0.vho

3.12KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ip/design_1_xlslice_1_0/design_1_xlslice_1_0.xci

4.68KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ip/design_1_xlslice_1_0/design_1_xlslice_1_0.xml

15.19KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ip/design_1_xlslice_1_0/sim/design_1_xlslice_1_0.vhd

3.16KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ip/design_1_xlslice_1_0/synth/design_1_xlslice_1_0.vhd

3.77KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ip/design_1_xlslice_2_0/design_1_xlslice_2_0.veo

2.89KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ip/design_1_xlslice_2_0/design_1_xlslice_2_0.vho

3.12KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ip/design_1_xlslice_2_0/design_1_xlslice_2_0.xci

4.68KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ip/design_1_xlslice_2_0/design_1_xlslice_2_0.xml

15.19KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ip/design_1_xlslice_2_0/sim/design_1_xlslice_2_0.vhd

3.16KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ip/design_1_xlslice_2_0/synth/design_1_xlslice_2_0.vhd

3.77KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ip/design_1_xlslice_3_0/design_1_xlslice_3_0.veo

2.89KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ip/design_1_xlslice_3_0/design_1_xlslice_3_0.vho

3.12KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ip/design_1_xlslice_3_0/design_1_xlslice_3_0.xci

4.68KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ip/design_1_xlslice_3_0/design_1_xlslice_3_0.xml

15.19KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ip/design_1_xlslice_3_0/sim/design_1_xlslice_3_0.vhd

3.16KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ip/design_1_xlslice_3_0/synth/design_1_xlslice_3_0.vhd

3.77KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ipshared/xilinx.com/basys_7_seg_v1_0/BASYS_7_seg.vhd

3.48KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ipshared/xilinx.com/blk_mem_gen_v8_3/hdl/blk_mem_gen_v8_3.vhd

20.79KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ipshared/xilinx.com/blk_mem_gen_v8_3/hdl/blk_mem_gen_v8_3_vhsyn_rfs.vhd

14.13MB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ipshared/xilinx.com/c_addsub_v12_0/hdl/c_addsub_v12_0.vhd

12.29KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ipshared/xilinx.com/c_addsub_v12_0/hdl/c_addsub_v12_0_vh_rfs.vhd

383.7KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ipshared/xilinx.com/c_counter_binary_v12_0/hdl/c_counter_binary_v12_0.vhd

10.6KB

125.74KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ipshared/xilinx.com/c_gate_bit_v12_0/hdl/c_gate_bit_v12_0.vhd

10.72KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ipshared/xilinx.com/c_gate_bit_v12_0/hdl/c_gate_bit_v12_0_vh_rfs.vhd

155.7KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ipshared/xilinx.com/c_reg_fd_v12_0/hdl/c_reg_fd_v12_0.vhd

8.91KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ipshared/xilinx.com/c_reg_fd_v12_0/hdl/c_reg_fd_v12_0_vh_rfs.vhd

31.94KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ipshared/xilinx.com/fifo_generator_v13_0/hdl/fifo_generator_v13_0.vhd

88.89KB

2.14MB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ipshared/xilinx.com/hex_to_7_seg_v1_0/Hex_to_7_Seg.vhd

1.1KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ipshared/xilinx.com/ila_v6_0/hdl/ila_v6_0_syn_rfs.v

260.86KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ipshared/xilinx.com/ila_v6_0/hdl/verilog/ila_v6_0_1_ila_in_ports_inc.v

58.99KB

7.72KB

932.54KB

144.03KB

10.78KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ipshared/xilinx.com/ltlib_v1_0/hdl/ltlib_v1_0_vl_rfs.v

87.65KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ipshared/xilinx.com/ltlib_v1_0/hdl/verilog/ltlib_v1_0_0_lib_function.v

7.55KB

7.34KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ipshared/xilinx.com/xbip_addsub_v3_0/hdl/xbip_addsub_v3_0.vhd

9.36KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ipshared/xilinx.com/xbip_addsub_v3_0/hdl/xbip_addsub_v3_0_vh_rfs.vhd

26.58KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ipshared/xilinx.com/xbip_counter_v3_0/hdl/xbip_counter_v3_0.vhd

9.56KB

127.52KB

10.56KB

84.71KB

139.27KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ipshared/xilinx.com/xbip_pipe_v3_0/hdl/xbip_pipe_v3_0.vhd

8.13KB

24.07KB

154.09KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ipshared/xilinx.com/xlslice_v1_0/xlslice.vhd

1.2KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ipshared/xilinx.com/xsdbm_v1_1/hdl/verilog/xsdbm_v1_1_1_icon2xsdb_inc.v

5.84KB

4.95KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ipshared/xilinx.com/xsdbm_v1_1/hdl/verilog/xsdbm_v1_1_1_inc.v

7.4KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ipshared/xilinx.com/xsdbm_v1_1/hdl/verilog/xsdbm_v1_1_xsdbm.v

171.85KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ipshared/xilinx.com/xsdbm_v1_1/hdl/xsdbm_v1_1_vl_rfs.v

166.87KB

5.84KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ipshared/xilinx.com/xsdbs_v1_0/hdl/verilog/xsdbs_v1_0_2_inc.v

7.4KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ipshared/xilinx.com/xsdbs_v1_0/hdl/xsdbs_v1_0_vl_rfs.v

36.29KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ui/bd_1f5defd0.ui

1.86KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/imports/Hex_to_7_Seg/Hex_to_7_Seg.vhd

1.1KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/imports/Hex_to_7_Seg/component.xml

6.47KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/imports/Hex_to_7_Seg/xgui/Hex_to_7_Seg_v1_0.tcl

205B

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.tmp/edit_ip_project.hw/webtalk/labtool_webtalk.log

406B

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.tmp/edit_ip_project.hw/webtalk/usage_statistics_ext_labtool.html

6.57KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.tmp/edit_ip_project.hw/webtalk/usage_statistics_ext_labtool.xml

6.06KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.tmp/edit_ip_project.hw/webtalk/xsim_webtallk.info

59B

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.xpr

8.81KB

~Get Your Files Here !/08 - Hardware Design Debugging and Verification/external-assets-links.txt

464B

~Get Your Files Here !/09 - Working with Soft Core Processors/001 Creating Your First Softcore Processor Project.mp4

15.9MB

~Get Your Files Here !/09 - Working with Soft Core Processors/001 Creating Your First Softcore Processor Project_en.srt

6.96KB

~Get Your Files Here !/09 - Working with Soft Core Processors/002 Add AXI Peripherals to Your MicroBlaze Processor.mp4

18.17MB

~Get Your Files Here !/09 - Working with Soft Core Processors/002 Add AXI Peripherals to Your MicroBlaze Processor_en.srt

6.78KB

~Get Your Files Here !/10 - High Level Synthesis Tool/001 High Level Synthesis Tool Introduction.mp4

29.6MB

~Get Your Files Here !/10 - High Level Synthesis Tool/001 High Level Synthesis Tool Introduction_en.srt

3.57KB

~Get Your Files Here !/11 - Programming the FPGA/001 Vivado Hardware Manager Introduction.html

1.29KB

~Get Your Files Here !/11 - Programming the FPGA/002 Prior to Programming Checklist.html

1.56KB

~Get Your Files Here !/11 - Programming the FPGA/003 Loading the Configuration File on the FPGA.mp4

7.63MB

~Get Your Files Here !/11 - Programming the FPGA/003 Loading the Configuration File on the FPGA_en.srt

3.37KB

~Get Your Files Here !/12 - Project Design Flow Example Using Vivado/001 Project Design Flow Walkthrough.mp4

37.14MB

~Get Your Files Here !/12 - Project Design Flow Example Using Vivado/001 Project Design Flow Walkthrough_en.srt

4.8KB

~Get Your Files Here !/12 - Project Design Flow Example Using Vivado/002 Project-Requirements.pdf

338.71KB

~Get Your Files Here !/12 - Project Design Flow Example Using Vivado/002 Step 1 - Acquire Project Requirements.html

1.73KB

~Get Your Files Here !/12 - Project Design Flow Example Using Vivado/003 Step 2 - Select FPGA Based on Requirements.html

1.84KB

~Get Your Files Here !/12 - Project Design Flow Example Using Vivado/004 Step 3 - Create Project in Vivado.mp4

7.53MB

~Get Your Files Here !/12 - Project Design Flow Example Using Vivado/004 Step 3 - Create Project in Vivado_en.srt

2.54KB

~Get Your Files Here !/12 - Project Design Flow Example Using Vivado/005 Step 4 - Add Existing Custom IP.mp4

48.76MB

~Get Your Files Here !/12 - Project Design Flow Example Using Vivado/005 Step 4 - Add Existing Custom IP_en.srt

16.7KB

~Get Your Files Here !/12 - Project Design Flow Example Using Vivado/006 Step 5 - Add Create Design Constraints.mp4

19.8MB

~Get Your Files Here !/12 - Project Design Flow Example Using Vivado/006 Step 5 - Add Create Design Constraints_en.srt

6.46KB

~Get Your Files Here !/12 - Project Design Flow Example Using Vivado/007 Step 6 - Simulate and Verify Design.mp4

18.68MB

~Get Your Files Here !/12 - Project Design Flow Example Using Vivado/007 Step 6 - Simulate and Verify Design_en.srt

6.72KB

~Get Your Files Here !/12 - Project Design Flow Example Using Vivado/008 Step 7 - Generate the FPGA Configuration File.mp4

9.75MB

~Get Your Files Here !/12 - Project Design Flow Example Using Vivado/008 Step 7 - Generate the FPGA Configuration File_en.srt

3.52KB

~Get Your Files Here !/12 - Project Design Flow Example Using Vivado/009 Step 8 – Program your Board to Verify Functionality.mp4

9.22MB

~Get Your Files Here !/12 - Project Design Flow Example Using Vivado/009 Step 8 – Program your Board to Verify Functionality_en.srt

4.12KB

~Get Your Files Here !/12 - Project Design Flow Example Using Vivado/Final_Project/Basys3_Master.xdc

13.14KB

~Get Your Files Here !/12 - Project Design Flow Example Using Vivado/Final_Project/Final_Project_Test_Bench.vhd

1.78KB

~Get Your Files Here !/12 - Project Design Flow Example Using Vivado/Final_Project/ip_repo/BASYS_7_seg/BASYS_7_seg.vhd

3.48KB

~Get Your Files Here !/12 - Project Design Flow Example Using Vivado/Final_Project/ip_repo/BASYS_7_seg/component.xml

14.15KB

~Get Your Files Here !/12 - Project Design Flow Example Using Vivado/Final_Project/ip_repo/BASYS_7_seg/doc/BASYS_7_seg_documentation.pdf

560.18KB

~Get Your Files Here !/12 - Project Design Flow Example Using Vivado/Final_Project/ip_repo/BASYS_7_seg/src/basys_image.PNG

9.92KB

~Get Your Files Here !/12 - Project Design Flow Example Using Vivado/Final_Project/ip_repo/BASYS_7_seg/xgui/BASYS_7_seg_v1_0.tcl

1.59KB

~Get Your Files Here !/12 - Project Design Flow Example Using Vivado/Final_Project/ip_repo/Hex_to_7_Seg/Hex_to_7_Seg.vhd

1.1KB

~Get Your Files Here !/12 - Project Design Flow Example Using Vivado/Final_Project/ip_repo/Hex_to_7_Seg/component.xml

6.47KB

~Get Your Files Here !/12 - Project Design Flow Example Using Vivado/Final_Project/ip_repo/Hex_to_7_Seg/xgui/Hex_to_7_Seg_v1_0.tcl

205B

~Get Your Files Here !/12 - Project Design Flow Example Using Vivado/Final_Project/ip_repo/PWM/PWM.vhd

1.77KB

~Get Your Files Here !/12 - Project Design Flow Example Using Vivado/Final_Project/ip_repo/PWM/component.xml

9.99KB

~Get Your Files Here !/12 - Project Design Flow Example Using Vivado/Final_Project/ip_repo/PWM/xgui/PWM_v1_0.tcl

2.07KB

~Get Your Files Here !/12 - Project Design Flow Example Using Vivado/Final_Project/ip_repo/binary_bcd/binary_bcd.vhd

3.21KB

~Get Your Files Here !/12 - Project Design Flow Example Using Vivado/Final_Project/ip_repo/binary_bcd/component.xml

12.13KB

~Get Your Files Here !/12 - Project Design Flow Example Using Vivado/Final_Project/ip_repo/binary_bcd/xgui/binary_bcd_v1_0.tcl

777B

~Get Your Files Here !/13 - Conclusion/001 Conclusion.mp4

10MB

~Get Your Files Here !/13 - Conclusion/001 Conclusion_en.srt

1.17KB

~Get Your Files Here !/Bonus Resources.txt

386B

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