Uninettuno - Elettronica dei sistemi digitali 11-20

Torrent Hash:
1A0A8A58AE49BEF168138BADAD75C20EBA7B8FD2
Number of Files:
10
Content Size:
1.45GB
Convert On:
2019-06-27
Magnet Link:
W3siaWQiOiJhZHN0X2JfTV8zMDB4NTAiLCJhZHNwb3QiOiJiX01fMzAweDUwIiwid2VpZ2h0IjoiNSIsImZjYXAiOmZhbHNlLCJzY2hlZHVsZSI6ZmFsc2UsIm1heFdpZHRoIjoiNzY4IiwibWluV2lkdGgiOmZhbHNlLCJ0aW1lem9uZSI6ZmFsc2UsImV4Y2x1ZGUiOmZhbHNlLCJkb21haW4iOmZhbHNlLCJjb2RlIjoiPHNjcmlwdCB0eXBlPVwidGV4dFwvamF2YXNjcmlwdFwiPlxyXG4gIGF0T3B0aW9ucyA9IHtcclxuICAgICdrZXknIDogJzdkMWNjMGUxYjk4MWM5NzY4ZGI3ODUxZmM1MzVhMTllJyxcclxuICAgICdmb3JtYXQnIDogJ2lmcmFtZScsXHJcbiAgICAnaGVpZ2h0JyA6IDUwLFxyXG4gICAgJ3dpZHRoJyA6IDMyMCxcclxuICAgICdwYXJhbXMnIDoge31cclxuICB9O1xyXG4gIGRvY3VtZW50LndyaXRlKCc8c2NyJyArICdpcHQgdHlwZT1cInRleHRcL2phdmFzY3JpcHRcIiBzcmM9XCJodHRwJyArIChsb2NhdGlvbi5wcm90b2NvbCA9PT0gJ2h0dHBzOicgPyAncycgOiAnJykgKyAnOlwvXC93d3cuYm5odG1sLmNvbVwvaW52b2tlLmpzXCI+PFwvc2NyJyArICdpcHQ+Jyk7XHJcbjxcL3NjcmlwdD4ifV0=
File Name
Size
11 - Porte logiche bipolari (I Parte) Esercitazione SPICE su invertitori CMOS in cascata; Richiami sul transistore bipolare; Caratteristica I - V del transistore.avi
148.31MB
W3siaWQiOiJleG9jX2JfUExBWSIsImFkc3BvdCI6ImJfUExBWSIsIndlaWdodCI6IjEiLCJmY2FwIjpmYWxzZSwic2NoZWR1bGUiOmZhbHNlLCJtYXhXaWR0aCI6ZmFsc2UsIm1pbldpZHRoIjpmYWxzZSwidGltZXpvbmUiOmZhbHNlLCJleGNsdWRlIjpmYWxzZSwiZG9tYWluIjpmYWxzZSwiY29kZSI6IjwhLS1cclxuPGEgaHJlZj1cImh0dHBzOlwvXC9zeW5kaWNhdGlvbi5keW5zcnZ0YmcuY29tXC9zcGxhc2gucGhwP2lkem9uZT0xOTYxMDkyJnJldHVybl91cmw9aHR0cHM6XC9cL3RlbGxtZS5wd1wvZ29cL2J0c1wiICBjbGFzcz1cImJ0biBidG4td2FybmluZ1wiIHRhcmdldD1cIl9ibGFua1wiPjxzcGFuIGNsYXNzPVwiZ2x5cGhpY29uIGdseXBoaWNvbi1wbGF5XCI+PFwvc3Bhbj4gUGxheSBOb3c8XC9hPlxyXG4tLT4ifV0=
12 - Porte logiche bipolari (II Parte) Analisi statica dellinvertitore RTL; Tempo di accumulo del transistore bipolare; Dinamica dellinvertitore RTL.avi
147.44MB
W3siaWQiOiJleG9jX2JfUExBWSIsImFkc3BvdCI6ImJfUExBWSIsIndlaWdodCI6IjEiLCJmY2FwIjpmYWxzZSwic2NoZWR1bGUiOmZhbHNlLCJtYXhXaWR0aCI6ZmFsc2UsIm1pbldpZHRoIjpmYWxzZSwidGltZXpvbmUiOmZhbHNlLCJleGNsdWRlIjpmYWxzZSwiZG9tYWluIjpmYWxzZSwiY29kZSI6IjwhLS1cclxuPGEgaHJlZj1cImh0dHBzOlwvXC9zeW5kaWNhdGlvbi5keW5zcnZ0YmcuY29tXC9zcGxhc2gucGhwP2lkem9uZT0xOTYxMDkyJnJldHVybl91cmw9aHR0cHM6XC9cL3RlbGxtZS5wd1wvZ29cL2J0c1wiICBjbGFzcz1cImJ0biBidG4td2FybmluZ1wiIHRhcmdldD1cIl9ibGFua1wiPjxzcGFuIGNsYXNzPVwiZ2x5cGhpY29uIGdseXBoaWNvbi1wbGF5XCI+PFwvc3Bhbj4gUGxheSBOb3c8XC9hPlxyXG4tLT4ifV0=
13 - Porte logiche TTL (I Parte) Schema elementare di invertitore TTL; Analisi della commutazione basso - alto in uscita; Caratteristica di trasferimento dellinv.avi
148.49MB
W3siaWQiOiJleG9jX2JfUExBWSIsImFkc3BvdCI6ImJfUExBWSIsIndlaWdodCI6IjEiLCJmY2FwIjpmYWxzZSwic2NoZWR1bGUiOmZhbHNlLCJtYXhXaWR0aCI6ZmFsc2UsIm1pbldpZHRoIjpmYWxzZSwidGltZXpvbmUiOmZhbHNlLCJleGNsdWRlIjpmYWxzZSwiZG9tYWluIjpmYWxzZSwiY29kZSI6IjwhLS1cclxuPGEgaHJlZj1cImh0dHBzOlwvXC9zeW5kaWNhdGlvbi5keW5zcnZ0YmcuY29tXC9zcGxhc2gucGhwP2lkem9uZT0xOTYxMDkyJnJldHVybl91cmw9aHR0cHM6XC9cL3RlbGxtZS5wd1wvZ29cL2J0c1wiICBjbGFzcz1cImJ0biBidG4td2FybmluZ1wiIHRhcmdldD1cIl9ibGFua1wiPjxzcGFuIGNsYXNzPVwiZ2x5cGhpY29uIGdseXBoaWNvbi1wbGF5XCI+PFwvc3Bhbj4gUGxheSBOb3c8XC9hPlxyXG4tLT4ifV0=
14 - Porte logiche TTL (II Parte) Caratteristiche di ingresso e di uscita; FAN OUT della porta; Potenza dissipata statica; Dinamica dellinvertitore; Porte NAND T.avi
145.34MB
W3siaWQiOiJleG9jX2JfUExBWSIsImFkc3BvdCI6ImJfUExBWSIsIndlaWdodCI6IjEiLCJmY2FwIjpmYWxzZSwic2NoZWR1bGUiOmZhbHNlLCJtYXhXaWR0aCI6ZmFsc2UsIm1pbldpZHRoIjpmYWxzZSwidGltZXpvbmUiOmZhbHNlLCJleGNsdWRlIjpmYWxzZSwiZG9tYWluIjpmYWxzZSwiY29kZSI6IjwhLS1cclxuPGEgaHJlZj1cImh0dHBzOlwvXC9zeW5kaWNhdGlvbi5keW5zcnZ0YmcuY29tXC9zcGxhc2gucGhwP2lkem9uZT0xOTYxMDkyJnJldHVybl91cmw9aHR0cHM6XC9cL3RlbGxtZS5wd1wvZ29cL2J0c1wiICBjbGFzcz1cImJ0biBidG4td2FybmluZ1wiIHRhcmdldD1cIl9ibGFua1wiPjxzcGFuIGNsYXNzPVwiZ2x5cGhpY29uIGdseXBoaWNvbi1wbGF5XCI+PFwvc3Bhbj4gUGxheSBOb3c8XC9hPlxyXG4tLT4ifV0=
15 - Porte Logiche TTL (III Parte) Reti di PULL-UP e PULL-DOWN; Porte logiche TTL Schottky; Porte TTL-S ad alta velocità o a basso consumo.avi
147.05MB
W3siaWQiOiJleG9jX2JfUExBWSIsImFkc3BvdCI6ImJfUExBWSIsIndlaWdodCI6IjEiLCJmY2FwIjpmYWxzZSwic2NoZWR1bGUiOmZhbHNlLCJtYXhXaWR0aCI6ZmFsc2UsIm1pbldpZHRoIjpmYWxzZSwidGltZXpvbmUiOmZhbHNlLCJleGNsdWRlIjpmYWxzZSwiZG9tYWluIjpmYWxzZSwiY29kZSI6IjwhLS1cclxuPGEgaHJlZj1cImh0dHBzOlwvXC9zeW5kaWNhdGlvbi5keW5zcnZ0YmcuY29tXC9zcGxhc2gucGhwP2lkem9uZT0xOTYxMDkyJnJldHVybl91cmw9aHR0cHM6XC9cL3RlbGxtZS5wd1wvZ29cL2J0c1wiICBjbGFzcz1cImJ0biBidG4td2FybmluZ1wiIHRhcmdldD1cIl9ibGFua1wiPjxzcGFuIGNsYXNzPVwiZ2x5cGhpY29uIGdseXBoaWNvbi1wbGF5XCI+PFwvc3Bhbj4gUGxheSBOb3c8XC9hPlxyXG4tLT4ifV0=
16 - Esercitazione SPICE su porte TTL Caratteristica di trasferimento di invertitori TTL; Analisi dinamica di porte TTL; Effetto delle capacità di carico sul tem.avi
149.23MB
W3siaWQiOiJleG9jX2JfUExBWSIsImFkc3BvdCI6ImJfUExBWSIsIndlaWdodCI6IjEiLCJmY2FwIjpmYWxzZSwic2NoZWR1bGUiOmZhbHNlLCJtYXhXaWR0aCI6ZmFsc2UsIm1pbldpZHRoIjpmYWxzZSwidGltZXpvbmUiOmZhbHNlLCJleGNsdWRlIjpmYWxzZSwiZG9tYWluIjpmYWxzZSwiY29kZSI6IjwhLS1cclxuPGEgaHJlZj1cImh0dHBzOlwvXC9zeW5kaWNhdGlvbi5keW5zcnZ0YmcuY29tXC9zcGxhc2gucGhwP2lkem9uZT0xOTYxMDkyJnJldHVybl91cmw9aHR0cHM6XC9cL3RlbGxtZS5wd1wvZ29cL2J0c1wiICBjbGFzcz1cImJ0biBidG4td2FybmluZ1wiIHRhcmdldD1cIl9ibGFua1wiPjxzcGFuIGNsYXNzPVwiZ2x5cGhpY29uIGdseXBoaWNvbi1wbGF5XCI+PFwvc3Bhbj4gUGxheSBOb3c8XC9hPlxyXG4tLT4ifV0=
17 - Porte logiche ECL (I Parte) Invertitore elementare in logica non saturata; Schema elettrico dell'invertitore ECL; Analisi dei livelli logici.avi
148.39MB
W3siaWQiOiJleG9jX2JfUExBWSIsImFkc3BvdCI6ImJfUExBWSIsIndlaWdodCI6IjEiLCJmY2FwIjpmYWxzZSwic2NoZWR1bGUiOmZhbHNlLCJtYXhXaWR0aCI6ZmFsc2UsIm1pbldpZHRoIjpmYWxzZSwidGltZXpvbmUiOmZhbHNlLCJleGNsdWRlIjpmYWxzZSwiZG9tYWluIjpmYWxzZSwiY29kZSI6IjwhLS1cclxuPGEgaHJlZj1cImh0dHBzOlwvXC9zeW5kaWNhdGlvbi5keW5zcnZ0YmcuY29tXC9zcGxhc2gucGhwP2lkem9uZT0xOTYxMDkyJnJldHVybl91cmw9aHR0cHM6XC9cL3RlbGxtZS5wd1wvZ29cL2J0c1wiICBjbGFzcz1cImJ0biBidG4td2FybmluZ1wiIHRhcmdldD1cIl9ibGFua1wiPjxzcGFuIGNsYXNzPVwiZ2x5cGhpY29uIGdseXBoaWNvbi1wbGF5XCI+PFwvc3Bhbj4gUGxheSBOb3c8XC9hPlxyXG4tLT4ifV0=
18 - Porte logiche ECL (II Parte) Margini di rumore dell'invertitore ECL; Effetti termici sui livelli logici e sui margini di rumore; Potenza dissipata.avi
148.67MB
W3siaWQiOiJleG9jX2JfUExBWSIsImFkc3BvdCI6ImJfUExBWSIsIndlaWdodCI6IjEiLCJmY2FwIjpmYWxzZSwic2NoZWR1bGUiOmZhbHNlLCJtYXhXaWR0aCI6ZmFsc2UsIm1pbldpZHRoIjpmYWxzZSwidGltZXpvbmUiOmZhbHNlLCJleGNsdWRlIjpmYWxzZSwiZG9tYWluIjpmYWxzZSwiY29kZSI6IjwhLS1cclxuPGEgaHJlZj1cImh0dHBzOlwvXC9zeW5kaWNhdGlvbi5keW5zcnZ0YmcuY29tXC9zcGxhc2gucGhwP2lkem9uZT0xOTYxMDkyJnJldHVybl91cmw9aHR0cHM6XC9cL3RlbGxtZS5wd1wvZ29cL2J0c1wiICBjbGFzcz1cImJ0biBidG4td2FybmluZ1wiIHRhcmdldD1cIl9ibGFua1wiPjxzcGFuIGNsYXNzPVwiZ2x5cGhpY29uIGdseXBoaWNvbi1wbGF5XCI+PFwvc3Bhbj4gUGxheSBOb3c8XC9hPlxyXG4tLT4ifV0=
19 - Porte logiche ECL (III Parte) e circuiti combinatori con porte standard Porte ECL 10k e 100k; Confronto tra le famiglie logiche CMOS, TTL ed ECL; Porte A-O-.avi
150.89MB
W3siaWQiOiJleG9jX2JfUExBWSIsImFkc3BvdCI6ImJfUExBWSIsIndlaWdodCI6IjEiLCJmY2FwIjpmYWxzZSwic2NoZWR1bGUiOmZhbHNlLCJtYXhXaWR0aCI6ZmFsc2UsIm1pbldpZHRoIjpmYWxzZSwidGltZXpvbmUiOmZhbHNlLCJleGNsdWRlIjpmYWxzZSwiZG9tYWluIjpmYWxzZSwiY29kZSI6IjwhLS1cclxuPGEgaHJlZj1cImh0dHBzOlwvXC9zeW5kaWNhdGlvbi5keW5zcnZ0YmcuY29tXC9zcGxhc2gucGhwP2lkem9uZT0xOTYxMDkyJnJldHVybl91cmw9aHR0cHM6XC9cL3RlbGxtZS5wd1wvZ29cL2J0c1wiICBjbGFzcz1cImJ0biBidG4td2FybmluZ1wiIHRhcmdldD1cIl9ibGFua1wiPjxzcGFuIGNsYXNzPVwiZ2x5cGhpY29uIGdseXBoaWNvbi1wbGF5XCI+PFwvc3Bhbj4gUGxheSBOb3c8XC9hPlxyXG4tLT4ifV0=
20 - Connessione ed interfacciamento tra porte logiche Logica cablata wired and e wired or; Porte tri-state; Interfacciamento tra famiglie logiche differenti.avi
149.86MB
W3siaWQiOiJleG9jX2JfUExBWSIsImFkc3BvdCI6ImJfUExBWSIsIndlaWdodCI6IjEiLCJmY2FwIjpmYWxzZSwic2NoZWR1bGUiOmZhbHNlLCJtYXhXaWR0aCI6ZmFsc2UsIm1pbldpZHRoIjpmYWxzZSwidGltZXpvbmUiOmZhbHNlLCJleGNsdWRlIjpmYWxzZSwiZG9tYWluIjpmYWxzZSwiY29kZSI6IjwhLS1cclxuPGEgaHJlZj1cImh0dHBzOlwvXC9zeW5kaWNhdGlvbi5keW5zcnZ0YmcuY29tXC9zcGxhc2gucGhwP2lkem9uZT0xOTYxMDkyJnJldHVybl91cmw9aHR0cHM6XC9cL3RlbGxtZS5wd1wvZ29cL2J0c1wiICBjbGFzcz1cImJ0biBidG4td2FybmluZ1wiIHRhcmdldD1cIl9ibGFua1wiPjxzcGFuIGNsYXNzPVwiZ2x5cGhpY29uIGdseXBoaWNvbi1wbGF5XCI+PFwvc3Bhbj4gUGxheSBOb3c8XC9hPlxyXG4tLT4ifV0=

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W3siaWQiOiJhZHN0X2JfTV8zMDB4NTAiLCJhZHNwb3QiOiJiX01fMzAweDUwIiwid2VpZ2h0IjoiNSIsImZjYXAiOmZhbHNlLCJzY2hlZHVsZSI6ZmFsc2UsIm1heFdpZHRoIjoiNzY4IiwibWluV2lkdGgiOmZhbHNlLCJ0aW1lem9uZSI6ZmFsc2UsImV4Y2x1ZGUiOmZhbHNlLCJkb21haW4iOmZhbHNlLCJjb2RlIjoiPHNjcmlwdCB0eXBlPVwidGV4dFwvamF2YXNjcmlwdFwiPlxyXG4gIGF0T3B0aW9ucyA9IHtcclxuICAgICdrZXknIDogJzdkMWNjMGUxYjk4MWM5NzY4ZGI3ODUxZmM1MzVhMTllJyxcclxuICAgICdmb3JtYXQnIDogJ2lmcmFtZScsXHJcbiAgICAnaGVpZ2h0JyA6IDUwLFxyXG4gICAgJ3dpZHRoJyA6IDMyMCxcclxuICAgICdwYXJhbXMnIDoge31cclxuICB9O1xyXG4gIGRvY3VtZW50LndyaXRlKCc8c2NyJyArICdpcHQgdHlwZT1cInRleHRcL2phdmFzY3JpcHRcIiBzcmM9XCJodHRwJyArIChsb2NhdGlvbi5wcm90b2NvbCA9PT0gJ2h0dHBzOicgPyAncycgOiAnJykgKyAnOlwvXC93d3cuYm5odG1sLmNvbVwvaW52b2tlLmpzXCI+PFwvc2NyJyArICdpcHQ+Jyk7XHJcbjxcL3NjcmlwdD4ifV0=
W3siaWQiOiJhZHN0X2JfUE9QVU5ERVIiLCJhZHNwb3QiOiJiX1BPUFVOREVSIiwid2VpZ2h0IjoiNTkiLCJmY2FwIjoiMiIsInNjaGVkdWxlIjpmYWxzZSwibWF4V2lkdGgiOmZhbHNlLCJtaW5XaWR0aCI6Ijc2OCIsInRpbWV6b25lIjpmYWxzZSwiZXhjbHVkZSI6ZmFsc2UsImRvbWFpbiI6ZmFsc2UsImNvZGUiOiI8c2NyaXB0IHR5cGU9J3RleHRcL2phdmFzY3JpcHQnIHNyYz0nXC9cL2luY3JlYXNpbmdseWNvY2tyb2FjaHBvbGljeS5jb21cL2RlXC9jOFwvZjRcL2RlYzhmNGVmM2MyZGU4NDVhN2FkNDAwZmVlYTc4MGUzLmpzJz48XC9zY3JpcHQ+In0seyJpZCI6ImNsaWNfYl9QT1BVTkRFUiIsImFkc3BvdCI6ImJfUE9QVU5ERVIiLCJ3ZWlnaHQiOiI2MCIsImZjYXAiOiIyIiwic2NoZWR1bGUiOmZhbHNlLCJtYXhXaWR0aCI6ZmFsc2UsIm1pbldpZHRoIjpmYWxzZSwidGltZXpvbmUiOmZhbHNlLCJleGNsdWRlIjpmYWxzZSwiZG9tYWluIjpmYWxzZSwiY29kZSI6IiJ9LHsiaWQiOiJqYXZfYl9QT1BVTkRFUiIsImFkc3BvdCI6ImJfUE9QVU5ERVIiLCJ3ZWlnaHQiOiI1MiIsImZjYXAiOiIxIiwic2NoZWR1bGUiOmZhbHNlLCJtYXhXaWR0aCI6ZmFsc2UsIm1pbldpZHRoIjpmYWxzZSwidGltZXpvbmUiOmZhbHNlLCJleGNsdWRlIjpmYWxzZSwiZG9tYWluIjpmYWxzZSwiY29kZSI6IjxzY3JpcHQ+XHJcbiQoZG9jdW1lbnQuYm9keSkub24oXCJjbGlja1wiLCBmdW5jdGlvbihldmVudCkge1xyXG4gIHdpbmRvdy5vcGVuKFwiaHR0cHM6XC9cL3RlbGxtZS5wd1wvZ29cL2phdlwiKTtcclxuICAkKHRoaXMpLm9mZihcImNsaWNrXCIpO1xyXG59KTtcclxuPFwvc2NyaXB0PiJ9XQ==